 | Select the Course Number to get further detail on the course. Select the desired Schedule Type to find available classes for the course. The Schedule Type links will be available only when the schedule of classes is available for the selected term. |
| ECE 33700 - ASIC Design Laboratory |
|
Credit Hours: 2.00. Introduction to standard cell design of VLSI (Very Large Scale Integration) digital circuits using the VHDL hardware description language (Very High Speed Integrated Circuits Hardware Description Language). Emphasis on how to write VHDL that will map readily to hardware. Laboratory experiments using commercial grade computer-aided design (CAD) tools for VHDL based design, schematic based logic entry, logic and VHDL simulation, automatic placement and routing, timing analysis, and testing. Typically offered Fall Spring.
0.000 OR 2.000 Credit hours Syllabus Available Levels: Undergraduate, Graduate, Professional Schedule Types: Distance Learning, Laboratory, Lecture, Practice Study Observation All Sections for this Course Offered By: School of Elec & Computer Engr Department: Electrical & Computer Engr Course Attributes: Upper Division May be offered at any of the following campuses: West Lafayette Learning Outcomes: 1. Understand and use major syntactic elements of VDHL - entities, architectures, processes, functions, common concurrent statements, and common sequential statements. 2. Design combinational logic in a variety of styles including: schematic, structural VHDL, and behavioral VHDL, as well as demonstrate an awareness of timing and resource usage associated with each approach. 3. Design common sequential functions: flip-flops, registers, latches, and state-machines. 4. Create a VDHL test bench and use it to test/verify a sequential VHDL design of moderate complexity. 5. Place, route, and verify timing of a standard cell design. 6. Draw, given commented VHDL code of moderate complexity, a corresponding RTL level block diagram. 7. Use, modify, and create scripts to control the synthesis process. 8. Use different design styles, constraints, and optimization options to achieve required synthesis results. 9. Explain the difference between various ASIC design approaches, - standard cell, full custom, and programmable devices. 10. Prepare functional and interface requirements for a sequential design project of the student's choosing. 11. Create the hierarchical decomposition of a sequential design. 12. Gain experience in the oral presentation of their work to others. 13. Work in a team and negotiate the division of labor. 14. Gain familiarity with the use and purpose of design reviews. 15. Prepare final design documentation sufficient for another engineer to use, test, or enhance the design. |
 |