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| ECE 33700 - ASIC Design Laboratory |
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Associated Term:
Fall 2020
Learning Outcomes: 1. Design combinational and sequential logic in a variety of styles and awareness of resource usage. 2. Use, modify, create scripts to control logic synthesis. 3. Create a test bench and use it to verify a design that incorporates multiple sequential blocks. 4. Place, route, and verify timing of an ASIC design. 5. Determine the RTL architecture implied by HDL code of moderate complexity. 6. Explain the difference between various ASIC and digital system design approaches - standard cell, full custom, and programmable device. Required Materials: Technical Requirements: |
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